1. Field of the Invention
This invention relates generally to a technique for manufacturing circuit boards with reduced defects and the resulting board, and more particularly to a technique for reducing board defects in manufacturing a high density board with thin dielectric layers, which layers are prone to have pinhole like defects.
2. Background Information
In the manufacture of circuit boards and circuit cards and chip carriers (sometimes collectively referred to as circuit boards herein) one common technique is to form successive layers of dielectric material with circuitry formed thereon which forms multi layer circuit boards. As the circuitry becomes more dense, and particularly as the layers of dielectric material become thinner, due to technological advances, the board becomes more prone to be defective due to defects in the material. For example, pin hole type defects in the dielectric material may cause unwanted circuit connections between one layer of electrical circuitry and the next adjacent layer of circuitry. This can occur when plating is taking place to form a layer of circuitry on a layer of dielectric material which overlays another layer of dielectric material having electrical circuitry thereon. If there is a pin hole defect extending through the dielectric material on which the circuitry is being formed, and the pin hole defect overlies electrical circuity there beneath, the plating process may cause the defect to be plated and thus establish an unwanted connection between two layers of circuitry. These defects can cause the scrapping of circuit boards late in the manufacturing process, which is costly. Thus it is desirable to reduce manufacturing defects in circuit boards due defects of the pin hole type in the layers of dielectric material.